The difficulties in scaling current computing technologies to meet energy efficiency and high performance demands, combined with the looming end of Moore’s law, is spurring widespread interest in the neuromorphic computing paradigm. The key component of neuromorphic networks is an analog nonvolatile memory device with tunable conductance, mimicking the biological synapse. Such nonvolatile memory devices are memristors, which were predicted by L. Chua in 1971  and implemented only a decade ago using RRAM . The reports of neuromorphic functionality based on pure memristive devices to achieve high density have so far been very limited, as demonstrated on small neuromorphic networks, by a pioneering research group led by D. Strukov in 2015 . However, memristive technology is still not mature enough for the very large-scale integration necessary to obtain practical value from neuromorphic networks. Remarkably, after a decade of intensive research, part of the pioneers of memristive devices are shifting the spotlight back towards nonvolatile floating-gate “synapse transistors,” which were proposed 30 years ago by C. Mead , utilizing their present technological maturity to deliver the demands of practical neuromorphic systems. Recently, a prototype three-layer mixed-signal neuromorphic network was implemented, using arrays of optimized embedded nonvolatile floating-gate cells redesigned from a commercial 180 nm NOR flash memory . But the large footprint, high switching voltages, number of terminals, endurance, expensive process, and the exponential I-V characteristics of a standard floating-gate transistor still constrain an upper bound on the overall performance.
In our work, we propose and experimentally demonstrate an innovative memristive floating-gate device that successfully combines the technological maturity of commercial floating-gate transistors and the conceptual novelty of the memristor, including high density and efficient functionality, as illustrated in Figure 1 and compared in Table I. Aiming to close the technological-functional gap between floating-gate and memristive devices as synapses in neuromorphic systems, we fabricated, for the first time, a two-terminal floating-gate transistor in a purely standard commercial CMOS process (no additional manufacturing masks). Our memristive device is gradually switched, similar to a standard floating-gate transistor, with optimized voltages and times, and linearized for small-signal voltages operating as a varying resistor. We show proof-of-concept neuromorphic applications on integrated arrays based on our device, including the spike-time-dependent-plasticity learning rule, vector-matrix-multiplication, associative memory, and supervised training for classification.
Our invention came about after a solid understanding of the theoretical basis of neuromorphic computing and technological capabilities combined with practical market needs, and in collaboration with TowerJazz Foundry.
We believe our paper will appeal to researchers in fields such as neuromorphic computing, machine learning and artificial intelligence (AI), emerging non-volatile memory devices, analog and mixed-signal circuit design, computational neuroscience, and others. By bringing AI closer to the edge, we believe our work will spur the development and commercialization of industry-level very large-scale integrated memristive neuromorphic circuits for energy-efficient machine learning acceleration and deep biological studies, and that it will help to align the research interests of several communities using similar standards.
 Chua, L.O. Memristor—The missing circuit element. IEEE Trans. Circuit Theory 18, 507–519 (1971).
 Strukov, D.B., Snider, G.S., Stewart, D.R. & Williams, R.S. The missing memristor found. Nature 453, 80–83 (2008).
 Prezioso, M. et al. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521, 61–64 (2015).
 Diorio, C., Hasler, P., Minch, A., & Mead, C. A single-transistor silicon synapse. IEEE Trans. Electron. Dev. 43, 1972–1980 (1996).
 Merrikh Bayat, F. et al. High-performance mixed-signal neurocomputing with nanoscale floating-gate memory cell arrays. IEEE Trans. Neural Netw. Learn. Syst. 29, 4782-4790 (2018).