Formulating 2D semiconductor inks for high-performance large-area electronics

A solution-processable 2D semiconducting MoS2 nanosheets ink for the scalable fabrication of high-performance thin-film electronics (transistors and logic gates) over a large area.
Formulating 2D semiconductor inks for high-performance large-area electronics

2D van der Waals thin film electronics

Solution-processable 2D semiconductor nanosheets may be processed into large-area thin films through continuous printing or roll-to-roll fabrications, representing promising building blocks for the scalable fabrication of thin films and the massive production of practical electronic devices. The broad-area dangling-bond-free contacts with pinning-free van der Waals (vdW) interfaces between 2D nanosheets can ensure optimized charge transport across the grain boundaries in the thin film, as initially demonstrated in our Bi2Se3 2D nanosheets-based thin films (Nano Lett. 2014, 14, 6547−6553). In contrast to the point-to-point contacts in 0D quantum dot thin films or 1D nanowire thin films that may be plagued by interfacial dangling bonds and chemical disorders, the clean vdW interface between 2D crystals promises high-performance thin-film electronics.

However, preparing such high-quality 2D semiconductor inks has been a long-standing challenge. The current MoS2 nanosheets ink materials are typically produced by the sonication-assisted direct liquid exfoliation (broad thickness distribution: 1-25 nm and unsatisfactory film quality; µ ~ 0.4 cm2·V-1·s-1, on/off ratio ~ 102), and Li/Na/K intercalation exfoliation approach (phase transition to metallic 1T structure; µ < 0.3 cm2·V-1·s-1, on/off ratio < 10). To date, the absence of high-quality semiconducting 2D ink materials serves as a major stumbling block to fully realizing the potential of 2D-nanosheets based thin-film electronics.

Manipulating the electron injection during the intercalation

In our recent work, we obtained the pure 2H-phase semiconducting MoS2 ink using the intercalation-based exfoliation approach. Our philosophy of preventing the undesired MoS2 phase transition to 1T structure during intercalation is to play with the dimension of intercalants. During the lithium intercalation process, the insertion of a large number of Li+ (LixMoS2: 1 Li+ and thus 1 e per MoS2, Eq. 1) leads to massive electron injection into the MoS2 crystal that induces the undesired semiconducting (2H) to metallic (1T) phase transition. And theoretical studies suggest that such phase transition only occurs when the electron injection exceeds a certain threshold (0.29 e per MoS2). To this end, we came up with the idea of intercalating 2D layered crystals (i.e. MoS2) with large-size quaternary ammonium molecules, such as tetraheptylammonium bromide (THAB). The bulky size of THAB molecules (d ~ 20 Å comparing with d < 2 Å for Li) naturally limits the number of molecules that can fit into the hosting 2D crystals and thus the number of electrons injected (0.02 e per MoS2, Eq. 2), which prevents the undesired phase transition into metallic 1T structure.

          MoS2 + xLi+ + xe- (Li+)xMoS2x-                  x≈ 1              (1)                        

          MoS2 + xTHA+ + xe- (THA+)xMoS2x-         x≈ 0.02        (2)                            

A relatively narrow thickness distribution (in contrast to the liquid exfoliation) was obtained in the semiconducting 2H-phase MoS2 nanosheets. The resulting ink material (up to ~ 10 mg/mL) can be processed into high-performance large-area thin-film transistors (µ ~ 10 cm2·V-1·s-1, on/off ratio ~ 106), through cost-effective and scalable solution-based deposition techniques. In addition, this exfoliation approach can be readily applied to a wide variety of 2D layered materials, including WSe2, Bi2Se3, NbSe2, In2Se3, Sb2Te3, and black phosphorus.

Integrated logic gates and computational circuits

The robust and high-yield (> 95%) fabrication of thin-film transistor (TFT) arrays readily enable the construction of a series of logic gates, including inverter, NAND, NOR, AND, and XOR logic gates. The successful realization of these diverse logic functions allows us to further construct computational circuits such as a half adder, which corresponds to the addition of two one-bit binary numbers. The experimental truth table clearly demonstrates that we have successfully implemented a basic logic computation.

Our study has thus enabled the scalable integration of complex logic computational circuits from solution-processed 2D materials, which is previously unattainable with other types of chemical intercalants (Li/Na/K and analogues) or liquid exfoliation (intensive and prolonged sonication in solvents). We hope our work will continually contribute to the advancement of 2D-material-based electronic circuits.

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Electrical and Electronic Engineering
Technology and Engineering > Electrical and Electronic Engineering
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