With its attractive properties, the two-terminal memristor device (also known as the resistance switch) is promising for a wide variety of applications including non-volatile memory and brain-inspired computing. Building high density memristor circuits becomes increasingly important to fully unleash the potential. The challenge lies in the fabrication of highly ordered and highly conductive nanoelectrode arrays that are individually accessible.

There are several nanofabrication approaches that are capable of making extremely small structures. One methodology, usually categorized as ‘bottom up’, relies on the growth of nanomaterials (for example, carbon nanotubes, graphene nanoribbons and dopant silicon nanowires) through gas or vapor decomposition processes at elevated temperatures. Although procedurally simple, it has been difficult to make ordered arrays from these materials. The other approach, namely ‘top-down’, makes nanostructures through a series of patterning, etching and deposition processes. By ‘top-down’ techniques, such as transfer printing and nanoimprinting, highly ordered arrays of metal nanowires have been fabricated. Nevertheless, it has been difficult for both approaches to make electrical contact to each wire so that all devices are randomly accessible. Furthermore, a common problem with all of these aforementioned nanomaterials is the significantly increased electrical resistance at the nanoscale, making them unsuitable as electrodes for the circuits.

We addressed these issues by developing a nanofin technology in which high aspect ratio platinum nanostructures, with individual copper contacts, are used as the electrodes. The nanofins are deposited on a sidewall of a trench in the substrate and isolated from each other with a layer of insulator. They are then polished to expose the edges – an array of alternating metal and insulator nanostructures. Two of such arrays orientated orthogonal to each other, with a layer of switching material deposited in between, make a crossbar array. Due to the high aspect ratio of the metal nanofins, the electrical resistance is very low. For example, a two nanometer platinum nanofin with three micrometer height has a resistance of 65 ohms per micrometer of length. This is 10,000 times more conductive than a single walled carbon nanotube of 1.38 nanometers in diameter.

A big challenge is to make a continuous platinum film that remains only a few atoms thin. Because of their high surface energy, metal atoms tend to agglomerate into islands, leaving a percolated network, or isolated metal clusters, on the dielectric surface. As a solution, a very thin germanium wetting layer deposited onto the dielectric before platinum helps create a continuous and smooth metal film, leading to the greatly improved electrical conductance. With this technique, we were able to make platinum electrode arrays of 1.5 nanometer width, and we projected that nanofins of one nanometer width are feasible.

Our working memristor arrays have a two nanometer feature size and six nanometer half pitch (pitch is the center to center distance of two wires). This translates into a packing density of 4.5 terabits per square inch. All of the memristors in the demo arrays show resistance switching behavior with tens of nanoamperes electric current. The densely packed crossbar arrays of individually accessible, extremely small memristors, provide a power-efficient solution for future information storage and processing.