Behind the Research: Optimizing Real-Time Thermal Imaging for Agricultural Automation
Published in Computational Sciences
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A deep dive into benchmarking lightweight YOLO architectures for okra maturity detection
Introduction
Agricultural automation faces a critical challenge: how can we develop inspection systems that are both highly accurate and fast enough for real-time processing? In our recent study published in The Journal of Supercomputing, my colleagues and I addressed this question by systematically benchmarking four state-of-the-art YOLO nano-variant object detection models for thermal imaging applications in okra maturity grading.
Why Thermal Imaging Matters
Traditional RGB-based inspection systems struggle under variable lighting conditions—a common reality in agricultural settings ranging from night harvesting to indoor packing facilities. Thermal imaging offers a compelling alternative by capturing temperature-dependent information that remains consistent regardless of ambient lighting. For okra specifically, thermal signatures reveal physiological differences in moisture content and thermal mass between maturity stages, providing a robust basis for automated quality assessment.
However, thermal imagery presents unique computational challenges. Single-channel intensity data, reduced texture information, and temperature-dependent contrast require specialized architectural considerations that haven't been systematically evaluated in prior research.
The Research Gap
While YOLO (You Only Look Once) architectures have been extensively benchmarked on RGB datasets such as COCO and ImageNet, comprehensive evaluation on thermal agricultural imagery remained absent from the literature. This gap is particularly significant because:
- Architectural innovations designed for RGB may not transfer effectively to thermal domains
- Real-time industrial sorting requires sub-50 millisecond inference latency
- Deployment on heterogeneous computing platforms (GPU vs. CPU) demands quantitative performance analysis
Our study addresses these gaps by evaluating YOLOv5n, YOLOv8n, YOLOv11n, and YOLOv12n across multiple performance dimensions.
Methodology Highlights
We developed a dual-source thermal dataset combining passive and active thermal imaging modalities. The active thermal approach—involving controlled preheating to 30°C—proved particularly important. Natural thermal contrast between adequately matured and overripe okra averages only 2.8°C under ambient conditions, which can be insufficient under variable environments. Controlled preheating amplifies this contrast to 4–8°C by exploiting maturity-dependent differences in thermal mass and cooling behavior.
Our experimental design incorporated rigorous statistical validation across five independent training runs, ensuring reproducibility and significance testing of observed performance differences. This methodological rigor is essential for drawing reliable conclusions in machine learning research.
Key Findings
Training Duration Dependency
One of our most significant findings relates to training efficiency. Under the resource-efficient 10-epoch protocol—reflecting rapid development scenarios—YOLOv8n achieved the highest detection accuracy (66.3% mAP@0.5–0.95), while YOLOv5n delivered comparable performance (66.1%) with superior computational efficiency.
However, extended training experiments revealed a critical insight: attention-based architectures (YOLOv11n and YOLOv12n) achieve higher peak accuracy (73.1% and 72.9% respectively) when training budgets permit 45–67 epochs. This performance ranking inversion suggests that architectural complexity translates to gains only with sufficient training iterations—a crucial consideration for practical deployment.
Platform-Specific Performance
Our benchmarking across heterogeneous computing platforms revealed distinct trade-offs:
- GPU deployment (NVIDIA T4 with TensorRT): YOLOv8n achieved 1.6 ms inference latency, supporting throughput exceeding 625 FPS—well above the ≥20 FPS requirement for real-time sorting
- CPU deployment (ONNX Runtime): YOLOv5n exhibited superior performance at 31.1 ms, making it optimal for edge and embedded scenarios
These findings provide practical guidance for selecting architectures based on deployment constraints.
Architectural Insights
Through gradient-weighted class activation mapping (Grad-CAM) analysis, we discovered that decoupled detection heads enable task-specific feature specialization. Classification branches focus selectively on thermal intensity gradients, while localization branches emphasize geometric boundaries—a design principle particularly beneficial for thermal imagery where diagnostic features are spatially distinct.
Ablation studies confirmed that mosaic augmentation improved detection performance by 6.2% without additional latency, while balanced loss weighting outperformed imbalanced configurations in this binary classification task.
Practical Implications
Our research demonstrates that thermal-based YOLO nano-variants are ready for integration into automated sorting pipelines, achieving 75 kg/min throughput with <2% background false positives. The system operates at sustained rates exceeding industrial requirements while maintaining high detection accuracy.
For practitioners, the key takeaway is this: model selection must jointly consider deployment constraints (inference latency, memory footprint) and available training resources (time budget, computational capacity). Simple architectures like YOLOv5n and YOLOv8n excel in rapid-iteration scenarios, while attention-based variants justify their complexity only when extended training is feasible.
Future Directions
Several promising research directions emerge from this work:
- Dataset expansion across cultivars, seasons, and environmental conditions to enhance model robustness
- Multi-class grading spanning the full maturity spectrum
- Multispectral fusion combining thermal and RGB modalities
- Knowledge distillation from transformer-based teachers to lightweight students
- Field deployment trials in commercial facilities for long-term validation
Conclusion
This systematic benchmark establishes quantitative baselines for thermal agricultural imaging and provides practical guidance for architecture selection. The identified strategies—anchor-free detection, decoupled heads, mosaic augmentation, and balanced loss weighting—are transferable to other crops and sensing modalities, offering strong potential for advancing automated agricultural inspection systems.
Article Citation: Ganapathy, M.R., Pugazhendi, P., Periasamy, S., Nagarajan, B. (2026). Benchmarking YOLO nano-architectures for real-time thermal imaging: application to okra maturity grading on heterogeneous computing platforms. The Journal of Supercomputing, 82:97. https://doi.org/10.1007/s11227-026-08226-w
Data Availability: The public thermal dataset is available at Mendeley Data. Code is available at the project GitHub repository.
I'm Dr. Pathmanaban Pugazhendi, an Assistant Professor at Easwari Engineering College, where I combine my passion for Computer Vision, Thermal Imaging, Deep Learning, and Edge AI to solve real-world problems in agriculture, food safety, and sustainable technology.
My Research Journey
My work has been cited over 410 times across various international journals, with a Total Author Impact Factor of 62.20. What drives me is the opportunity to bridge the gap between cutting-edge AI research and practical applications that make a tangible difference.
In Agricultural Technology & Food Science:
- I develop AI-powered systems for precision agriculture, helping farmers detect diseases and defects in crops like guava, sugarcane, and sapota
- I use thermal imaging to assess fruit quality post-harvest, reducing food waste and improving safety
- My recent work includes uncertainty-aware deep learning models that make agricultural AI more reliable and trustworthy
In Sustainable Engineering:
- I apply machine learning to optimize engine performance using alternative fuels like biodiesel and ethanol-water blends
- I'm working on intelligent battery management systems for electric vehicles
- My research explores how AI can accelerate our transition to renewable energy
In Computer Vision & AI:
- I specialize in developing lightweight deep learning models (like YOLO architectures) that can run on edge devices
- I'm particularly interested in making AI accessible for resource-constrained environments—bringing powerful technology to where it's needed most, not just where computational resources are abundant
What Drives My Work
I believe AI should be practical, deployable, and accessible. That's why much of my research focuses on developing efficient models that work in real-world conditions—whether it's detecting bread contamination using thermal imaging, identifying weld defects in manufacturing, or helping farmers spot crop diseases early.
My work has been published in top-tier Q1 journals including Journal of Food Engineering (IF: 5.8), Scientific Reports (IF: 3.9), and Trends in Food Science & Technology (IF: 15.4), but what matters most to me is seeing these technologies actually being used to solve problems.
Looking Forward
I'm currently focused on advancing Edge AI technologies—developing intelligent systems that can make split-second decisions without needing constant cloud connectivity. From smart farming tools to industrial quality control systems, I'm excited about building AI that works anywhere, for anyone.
I'm always open to collaborations, discussions, and connecting with fellow researchers, students, and industry professionals who share a passion for applied AI and sustainable technology.
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The Journal of Supercomputing
The Journal of Supercomputing publishes papers on the technology, architecture and systems, algorithms, languages and programs, performance measures and methods, and applications of all aspects of supercomputing.
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Special Issue on New Challenges for Heterogeneous Computing with Emerging HPC Devices
Call for Papers
High-Performance Computing (HPC) has traditionally embraced heterogeneity through the integration of multi-core CPUs, GPUs, and FPGAs within parallel and distributed computing systems. This established landscape is now being enriched by emerging technologies that further diversify the computational ecosystem: from specialized AI accelerators such as Tensor Processing Units (TPUs) and Neural Processing Units (NPUs) that bring unprecedented efficiency for machine learning workloads, to RISC-V processors that introduce open-source, customizable architectures that enable new design possibilities across the computing spectrum, up to low-power devices for edge computing aimed to extend HPC capabilities to resource-constrained environments at the network edge.
The fundamental challenge in this increasingly diverse landscape is the integration of multiple forms of parallelism. Achieving high performance and energy efficiency requires seamlessly combining and orchestrating different parallelism paradigms. Each hardware component operates optimally under different parallelism strategies, presenting distinct memory hierarchies, programming models, instruction sets, and performance characteristics. Successfully exploiting this heterogeneity demands methodologies, algorithms and software tools that can intelligently integrate these diverse parallelism forms into unified, efficient execution strategies. Achieving effective integration across highly heterogeneous HPC systems encompasses several critical issues, as it involves several deeply interconnected challenges. At the most fundamental level, managing large-scale parallelism across millions of heterogeneous computing units demands sophisticated coordination mechanisms that are both robust and scalable. Closely related to this is the need to carefully orchestrate data movement and communication across diverse memory systems and interconnects, since even minor inefficiencies in this regard can quickly become severe performance bottlenecks.
The situation is further complicated by workload balancing, which grows increasingly difficult when the computing elements involved exhibit widely varying capabilities and performance profiles. At the same time, any solution must ensure performance portability across different hardware configurations, and this must be achieved without compromising the energy efficiency that originally motivated the adoption of specialized hardware. Finally, and perhaps most critically from a usability standpoint, programming abstractions must be designed to shield application developers from the underlying complexity of the system, while still preserving the ability to exploit hardware-specific optimizations whenever the situation demands it.
Topics of Interest
We welcome submissions that address the integration and combination of multiple forms of parallelism in heterogeneous HPC systems. Topics include, but are not limited to:
• Hybrid and hierarchical parallel algorithms combining distributed, shared-memory, and accelerator-based parallelism
• Architecture-aware algorithm design and auto-tuning techniques exploiting multiple parallelism paradigms
• Mixed precision algorithms and adaptive precision techniques for heterogeneous accelerators
• Task scheduling, load balancing, and workflow orchestration integrating different types of computing elements
• Performance analysis, scalability models, and performance portability across heterogeneous platforms
• GPU computing, AI accelerators (TPUs, NPUs), and FPGA-based acceleration integrated with traditional computing
• RISC-V architectures, algorithms, software, and applications in heterogeneous systems
• Edge computing devices and edge-cloud continuum architectures with integrated heterogeneous resources
• Programming environments, tools, compiler techniques and frameworks for unified exploitation of heterogeneous resources
• Resource management, virtualization, and synchronization mechanisms across different parallelism paradigms
• Multi-level cache management, memory hierarchy optimization, and data movement coordination
• Fault tolerance, power management, and energy-efficient computing in heterogeneous systems
• Scientific workflow parallelization and execution on heterogeneous architectures
• Scientific computing, AI/ML workloads, and real-time applications on heterogeneous HPC platforms
• Large-scale simulations and computational science applications leveraging heterogeneous accelerators
Submission Guidelines
This special issue aims to collect extended papers from the 8th Workshop on Models, Algorithms and Methodologies for Hybrid Parallelism in new HPC Systems (MAMHYP-26), held in Poznań, Poland, from August 30th to September 3rd, 2026, jointly with the Parallel Processing and Applied Mathematics (PPAM 2026) conference, as well as other original contributions spanning the HPC spectrum and relevant to the topics of the special issue.
Furthermore, submissions must follow these guidelines:
• All papers will be peer-reviewed and accepted based on their scientific merit, novelty, and relevance to the special issue topics. At least one of the guest editors will review primarily the submissions.
• Submissions should present original research that has not been published or under review at another journal or conference at any time during the review process elsewhere.
• Extended versions of conference papers are welcome, provided that the journal submission contains at least 50% new material compared to the conference version, for example in the form of novel algorithms, additional experiments, or qualitative and quantitative comparisons. Authors should clearly describe the new contributions
• Manuscripts should be prepared according to the journal's author’s guidelines (formatting, structure, length requirements).
• Submit your manuscript through the journal's online submission system, clearly indicating that it is for this special issue.
Important Dates
• Submission deadline: January 2027
• First review round: March 2027
• Submission deadline for revised manuscripts: April 2027
• Final decision: May 2027
• Expected publication: Summer 2027
Publishing Model: Hybrid
Deadline: Jan 31, 2027
Section - Architectures, Systems and Hardware Security
All aspects of high-performance hardware and architectures, including optimizing and evaluating processors, systems issues, and security, especially at the hardware level and sustainability of systems.
Topics include but not limited to the following:
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• Architectural support for programming languages or software development.
• Architectures to support extremely heterogeneous composable systems (e.g., chiplets)
• Design-space exploration/performance projection for future systems
• Evaluation and measurement on testbed or production hardware systems
• Hardware acceleration of containerization and virtualization mechanisms for HPC
• Interconnect technologies, topology, switch architecture
• I/O architecture/hardware and emerging storage technologies
• Memory systems: caches, memory technology, non-volatile memory, memory system architecture (to include address translation for cores and accelerators)
• Multi-processor architecture and micro-architecture (e.g., reconfigurable, vector, stream, dataflow, GPUs, and custom/novel architecture)
• Sustainable design aspects, including power and energy efficiency and power-management strategies
• Resilience, error correction, high availability architectures
• Scalable and composable coherence (for cores and accelerators)
• Secure architectures, side-channel attacks, and mitigation, covering all attack vectors, including all forms of side-channel attacks, piracy, reverse engineering, tampering, and hardware Trojan attacks, including countermeasures at different stages of system design - i.e., architecture definition, design, validation, and deployment
• The security of hardware and system security at all levels of abstraction
• Interactions between hardware and systems, and between hardware and firmware/software, including in the context of security and trust
• Software/hardware co-design, domain-specific language support
• Interactions among architectures, compilers, programming languages, and operating systems
Architectures, Systems and Hardware Security research relates to multiple United Nations Sustainable Development Goals (SDGs) through advances in health care, education, and energy, among other fields. This Section particularly welcomes submissions related to SDG 9 “Industry, Innovation, And Infrastructure.”
An essential aspect of supercomputing involves solving computer-intensive problems. Paper submissions are expected to address problems that require significant computational resources.
Publishing Model: Hybrid
Deadline: Ongoing
