Frequently rewritten memory requires low operating voltage, fast switching and high endurance. Ferroelectric hafnium–zirconium oxide (HZO) is attractive because it stores information in polarization states that can persist after the applied voltage is removed. However, accelerating polarization reversal generally requires a stronger electric field, increasing electrical stress and shortening device lifetime. Thinning the ferroelectric can lower the operating voltage, but interfacial voltage loss and electrode screening become increasingly important. In our Nature Communications study, we address this voltage–speed–endurance tradeoff by engineering the TiN electrodes and their interfaces with 5 nm HZO.

We retained an equimolar Hf:Zr composition and focused on how the applied voltage reaches the ferroelectric. Using plasma-enhanced atomic layer deposition, we obtained (111)-textured TiN electrodes with nitrogen-rich surfaces that resisted oxidation. This suppressed unwanted interfacial oxide formation and reduced voltage loss at the electrode–HZO interface. The resulting capacitors reached saturated polarization switching at 0.6 V, with a switched remanent polarization window above 30 μC cm⁻². We also examined how finite screening of polarization charge by the electrodes contributes to the low external switching field. The resulting depolarization field opposes the initial polarization and can assist its reversal. Accounting for this internal field recovers Kay–Dunn-like thickness scaling, reconciling the low measured coercive field with the underlying scaling relation.

Switching kinetics measurements on conditioned 25 μm² capacitors gave characteristic 50% switching times of about 40 ns at 0.6 V and 8 ns at 1 V. At both voltages, cycling tests reached one trillion bipolar cycles without hard electrical breakdown, with the two polarization states still distinguishable. These results show that fast polarization reversal and substantial cycling tolerance can coexist at low voltage. We also measured switching across capacitor areas from 40,000 down to 25 μm². Smaller capacitors switched faster, consistent with a reduced contribution from rare, slowly switching regions. Extrapolating this area dependence suggests sub-nanosecond to low-nanosecond switching at DRAM-relevant footprints, depending on voltage, providing a target for future direct nanoscale measurements.

We then explored how these capacitor characteristics could support a memory architecture. The proposed common-plate ferroelectric RAM (CP-FeRAM) uses one transistor and one capacitor per cell with a fixed common-plate bias. We fabricated a 15-capacitor common-plate test structure that showed closely matched polarization responses after conditioning, and used calibrated circuit simulations to evaluate the proposed readout. In the idealized long-stand-by condition, after the linear stored-charge contrast has disappeared, retained polarization still produces a state-dependent signal. At a 1.1 V data supply, simulations using a (300 nm)² capacitor and a 20 fF bit-line load gave a sensing margin of about 200 mV. Readout is destructive and requires write-back, while the polarization-based signal offers a potential route to reducing refresh demands in a DRAM-like architecture.

The central advance is the combination of low voltage, rapid polarization reversal and cycling tolerance in an ultrathin capacitor, together with a readout concept that exploits the polarization left after charge relaxation. This links electrode and interface engineering to a specific memory opportunity: frequently rewritten, DRAM-like cells with polarization-based sensing. The experimental capacitor results and simulated CP-FeRAM operation provide complementary foundations for this direction. Demonstrating both in an integrated transistor–capacitor array is the next step toward practical memory hardware.

For more details, please refer to the published article in Nature Communications:

https://doi.org/10.1038/s41467-026-78705-4