Scaling aligned carbon nanotube transistors to a sub-10 nm node

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Carbon nanotubes have attracted significant interest due to their unique geometric configuration and electronic properties. They have demonstrated excellent performance and scaling behavior, surpassing traditional silicon CMOS transistors. Previous challenges in scalable fabrication have been overcome through advancements in semiconducting purity and alignment of CNT materials. Aligned carbon nanotubes (A-CNT) FETs with scaled gate lengths have been achieved, exhibiting practical performance comparable to silicon transistors. However, the large contacted gate pitch (CGP) of typical A-CNT FETs has limited their integration density and prevented the realization of predicted advantages.

 In our recent study published in Nature Electronics, we fabricated A-CNT FETs with a contacted gate pitch of 175 nm, achieved by scaling the gate length and contact length to 85 nm and 80 nm, respectively. Remarkably, the A-CNT FET exhibited an impressive on-current of 2.24 mA μm-1 and a peak transconductance of 1.64 mS μm-1, surpassing the size and electronic performance of silicon 45 nm node transistors (Fig.1).

Figure 1 | CGP scaling of top-gated A-CNT FETs for a 90 nm node. a, Schematic of CGP scaling. Lcon, Lg, Lsp and Wch represent the device contact length, gate length, spacer length and channel width, respectively. To scale the CGP, Lcon, Lg, and Lsp must be simultaneously reduced. b, TEM image of the cross section of A-CNTs. The inset shows an SEM image of the same film. Scale bar for the inset: 500 nm. c, False-color SEM image of three top-gated A-CNT FETs in series with shared source/drain contacts. A CGP of 175 nm is achieved with an Lcon of 80 nm and an Lg of 85 nm. Scale bar: 100 nm. d, e, Transfer characteristics (d) and output characteristics (e) of the top-gated A-CNT FET with a CGP of 175 nm. Vgs is varied from -2.2 V to 3.0 V with a step of 0.4 V from top to bottom.

Furthermore, we showed a six-transistor static random-access memory (SRAM) cell by these ultra-scaled A-CNT FETs, demonstrating a total area (0.976 μm2) comparable to the 90 nm node (1 μm2) of silicon CMOS technology. Additionally, the A-CNT SRAM cells consumed significantly less power compared to their silicon counterparts. Overall, the 90 nm node A-CNT technology exhibited higher integration density and performance than the 90 nm node of silicon technology and holds promise for further advancements (Fig.2).

 

Figure 2 | Ultrascaled 6T-SRAM cell based on 90 nm node A-CNT FETs. a, Circuit diagram of the 6T-SRAM cell based on A-CNT FETs. b, False-color SEM image of a representative 6T-SRAM cell with a CGP of 175 nm and an area of 0.976 μm2 for the 90 nm CNT technology node. Scale bar: 200 nm. c, Read margin characterization of the 6T-SRAM cell in b. d, Write margin characterization of the 6T-SRAM cell in b. e, Benchmarking the ultrascaled A-CNT 6T-SRAM cell in b with silicon 130 nm , 90 nm and 45 nm technology nodes for gate length, CGP and SRAM cell area. f, Comparison of state-of-the-art CNT technology reported in this work with silicon technology and 2D materials (MoS2, WSe2). Both the CGP and gm are benchmarked for various Lg.

To further enhance the performance and reduce dependence on the contact length, we introduced a full-contact structure between the metal and nanotubes. The full-contact structure combined the carrier injection mechanism of side contact and end contact, i.e., the carriers can be injected from the metal to CNTs at the side (length-dependent) and at the edge (length-independent). Therefore, the full-contact A-CNT/metal junction exhibited lower contact resistance than the side-contact or end-contact junctions while maintaining a weaker contact length dependence. This enables aligned CNT FETs to be further downscaled to CGP below 55 nm (corresponding to the 10 nm technology node), while outperforming 10 nm node silicon transistors due to their high carrier mobility and Fermi velocity. These results illustrated the potential of A-CNT FETs for high-performance digital ICs at sub-10 nm nodes and provides flexibility for the trade-off between the gate length and contact length for further whole downsizing (Fig.3).

 

Figure 3 | sub-10 nm A-CNT FETs with a full-contact structure. a, Schematics of the silicon planar structure, CNT side-contact structure, and CNT full-contact structure. b, Rc versus Lcon for both the side-contact structure (blue) and full-contact structure (red). c, SEM and cross-sectional TEM image of an ultrascaled A-CNT FET with a CGP of 61 nm, an Lg of 35 nm and an Lcon of 16 nm. Scale bar of the SEM image: 200 nm; of the TEM image: 100 nm. d, Output characteristics of A-CNT FETs and comparison with the silicon PMOS FET of the 10 nm technology node. e, Comparison of Ion at various CGP for A-CNT FETs in this work with that for other reported A-CNT FETs and silicon technology. f, Benchmarking the injection velocity of the aligned CNT arrays (all extracted by the VS model for CNT FETs) with that of Si FETs. g, Comparison of Ion versus Ioff at different Vds (increasing from left to right) for A-CNT FETs in this work with that for other reported A-CNT FETs and silicon technology. Note that here, Ion is the maximum on-current at the highest gate overdrive and Ioff is the minimum off-current.

More details on this study can be found in our recent article " Scaling aligned carbon nanotube transistors to a sub-10 nm node " published in Nature Electronics. (https://www.nature.com/articles/s41928-023-00983-3)

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