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VdW polarity-engineered 3D integration of 2D complementary logic

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Go to the profile of Zheng Vitto HAN
Zheng Vitto HAN
Professor, Shanxi University
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Nature
Nature Nature

Van der Waals polarity-engineered 3D integration of 2D complementary logic - Nature

We develop a method for high-density vertical stacking of active-device multi-layers, implementing memory and logic functions, using unique VIP-FETs where a van der Waals intercalation layer modulates the p- or n-type nature of the FETs.

This cartoon video describes the mechanism of the van der  Waals polarity-engineering of a 2D semiconductor. The n-type MoS2 transistor can be readily shifted into p-type, simply by being brought into contact with a few-layered CrOCl. Such interfacial coupling (with a quantum origin of e-e interaction) can lead to 2D p-FETs with low hysteresis, high ON current, as well as high ON-OFF ratio. The research paper "Van der Waals polarity-engineered 3D integration of 2D complementary logic" is published in Nature.

Go to the profile of Zheng Vitto HAN
Zheng Vitto HAN
Professor, Shanxi University

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